The scaling of integrated circuits is a constant effort. With circuits becoming smaller and faster, improvement in the device drive current of metal-oxide-semiconductor (MOS) devices becomes more important. The device drive current is closely related to the ratio of gate width to gate length and to carrier mobility. Shortening poly-gate length and increasing carrier mobility can improve the device drive current. Gate length reduction is an on-going effort in order to shrink circuit size. However, due to the short channel effect, the gate-width to gate-length ratio, which directly affects the device drive current, is hard to increase. In order to further improve device drive current, enhancing carrier mobility has also been explored.
Germanium and the compound materials of group III and group V elements (such as GaAs, InP, GaN, also known as III-V compound materials) are among the materials that can provide improved carrier mobility. Germanium is a commonly known semiconductor material. The electron mobility and hole mobility of germanium are greater than that of silicon, hence making germanium an excellent material in the formation of integrated circuits, particularly for forming PMOS devices. However, in the past, silicon gained more popularity since its oxide (silicon oxide) is readily usable in the gate dielectric of MOS devices. The gate dielectrics of the MOS devices can be conveniently formed by thermal oxidation of silicon substrates. The oxide of germanium, on the other hand, is soluble in water, and hence is not suitable for the formation of gate dielectrics. With the use of high-k dielectric materials in the gate dielectrics of MOS transistors, the convenience provided by the silicon oxide is no longer a big advantage, and hence germanium is re-examined for use in integrated circuits. On the other hand, III-V compound materials have high electron mobility, and hence are suitable for forming NMOS devices.
The integration of III-V compound materials and/or germanium with silicon substrates, however, has resulted in difficulties. These materials have significant lattice mismatch with silicon substrates, and hence when formed on the silicon substrates, will have a high amount of crystal defects such as dislocations. Conventionally, buffer layers are used to reduce the dislocations. For example, in order to provide an InGaAs quantum well channel for NMOS devices, a GaAs buffer layer having a thickness of 2 μm is grown on a silicon substrate. An InAlAs buffer layer having a thickness of 1.2 μm is further grown on the GaAs buffer layer, followed by the growth of the InGaAs layer. However, this scheme suffers from drawbacks. First, the buffer layers that have a combined thickness of 3.2 μm are too thick for the integration of NMOS and PMOS devices. The PMOS devices may be lower than the NMOS devices by 3.2 μm, resulting in process difficulties. Second, the InGaAs layer is not suitable for forming PMOS devices, and hence an additional layer may need to be formed on the InGaAs layer for forming the PMOS devices. This results in further increases in the manufacturing cost. New methods are thus needed to solve the above-discussed problems.